Francisco D. Igual is an Associate Professor at Universidad Complutense de Madrid, Spain. He received a PhD degree in Computer Science from Universitat Jaume I de Castellón, Spain, in 2011. He has participated in different national and international research and technology transfer projects, both as a researcher and as a Principal Investigator. He has published more than 80 journal and conference papers in the field of HPC, specifically covering topics such as architecture-aware code optimization for numerical linear algebra libraries, specific- and general-purpose accelerators exploitation and task scheduling. He is serving as a program committee member for many relevant conferences in the field of HPC and Computer Arhictecture.