Euro-Par 2024 | Track 3: Architectures and Accelerators | International European Conference on Parallel and Distributed Computing Track 3: Architectures and AcceleratorsEuro-par

Track 3 - Architectures and Accelerators

Chairs

Program Committee

  • José L. Abellán, Universidad de Murcia
  • Giovanni Agosta, Politecnico di Milano
  • Davide Bertozzi, University of Manchester
  • Mauricio Breternitz, Instituto Universitário de Lisboa
  • Xing Cai, Simula Research Laboratory
  • José Cano, University of Glasgow
  • Joao Cardoso, University of Porto
  • Jorge Luis Chacon Velasco, Universidad Industrial de Santander
  • Alex Delis, University of Athens
  • Toshio Endo, Tokyo Institute of Technology
  • Wuchun Feng, Virginia Tech
  • Holger Fröning, University of Heidelberg
  • Jorge G. Barbosa, University of Porto
  • Toshihiro Hanawa, Information Technology Center, The University of Tokyo
  • Koji Inoue, Kyushu University
  • Magnus Jahre, Norwegian University of Science and Technology
  • Christoph Kessler, Linköping University
  • Ryohei Kobayashi, University of Tsukuba
  • Hatem Ltaief, King Abdullah University of Science and Technology
  • Esteban Mocskos, UBA
  • Jose Manuel Monsalve Diaz, Argonne National Labs
  • Akira Naruse, NVIDIA
  • Francesca Palumbo, University of Cagliari
  • Chang Hyun Park, Uppsala University
  • Oscar Plata, University of Malaga
  • Carlos Reaño, Universitat de València
  • Julio Sahuquillo, Universitat Politècnica de València
  • Shinji Sumimoto, The University of Tokyo
  • Hiroyuki Takizawa, Tohoku University
  • Keita Teranishi, Oak Ridge National Laboratory
  • Christian Terboven, RWTH Aachen University
  • Samuel Thibault, LaBRI, Université Bordeaux 1, France
  • Pedro Trancoso, Chalmers University of Technology
  • Georgios Vavouliotis, Computing Systems Lab, Huawei Zurich Research Center
  • Michele Weiland, EPCC, The University of Edinburgh
  • Roman Wyrzykowski, Czestochowa University of Technology
  • Kazutomo Yoshii, Argonne National Laboratory

Focus

  • Architectures for instruction-level and thread-level parallelism
  • Manycores, multicores, accelerators, domain-specific and special-purpose architectures, reconfigurable architectures
  • Cloud and HPC storage architectures and systems
  • Memory technologies and hierarchies
  • Exascale system designs; data center and warehouse-scale architectures
  • Novel big data architectures
  • Parallel I/O and storage systems
  • Power-efficient and green computing systems
  • Resilience, security, and dependable architectures
  • Software architectures spanning IoT/Edge, Fog, Cloud, 5G and HPC computing
  • Processing in Memory and Near-Memory Processing
  • Interconnect/memory architectures
  • Post Moore era systems: neuromorphic, quantum, hybrid, ...

In cooperation

Organized by

Supported by

Awards support